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PCIe Gen 5 CEM Connector & Add-In Card PCB Design Optimizations
DesignCon 2019 will offer more than 100 technical sessions, panel discussions, and tutorials spanning 15 tracks over the 3-day conference program. If you have purchased an All Access or 2-Day pass, you will be able to attend these sessions.
Amphenol is proud to announce that Yifan Huang and Stephen Smith will present a technical paper titled “PCIe Gen 5 CEM Connector and Add-In Card PCB design optimizations” at DesignCon 2019. Li Ying, from Nvidia, will present along with the Amphenol team regarding Nvidia’s high-end 32Gb/s GPU add-in card design. This paper is part of Track 14: Modeling & Analysis of Interconnects, and will be presented on, January 30, 2019, Wednesday from 2:50 PM - 3:30 PM at Ballroom A, Santa Clara Convention Center, CA.
The PCIe Gen 5 channel data-rate of 32GT/s requires a better mating connector, an AIC with improved PCB material, optimized vias, and alternative trace routings. The Gen 5 surface-mount connector mates with the smaller gold edge fingers with a shorter wipe distance to achieve loss and crosstalk targets at twice the Gen 4 Nyquist frequency. AIC microstrip or stripline routings, via choices, ac capacitor mounting, and their effects are optimized for overall channel performance. AIC lead-in trace region to the connector is re-designed to improve the impedance match to the CEM connector. Measurements of a connector prototype with improved AIC validate the work.
PCIe Gen 5 Card Electro-Mechanical (CEM) connector is backward-compatible and mates to an Add-In Card (AIC) with smaller edge fingers that have a shorter wipe distance. The AIC design choices between microstrip and stripline traces are made to balance loss, crosstalk and mode conversion for optimizing the full channel performance.
Visit Amphenol at booth #731 to get more information on this and other innovative product.